The present invention relates generally to integrated circuit (IC) designs, and more particularly to a memory macro with irregular edge cells.
The rapid growth in complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist or automate most steps of the design process. A typical circuit design contains hundreds of thousands or millions of individual pieces or “leaf cells” or “cells.” Such design is too large for a circuit designer or even a team of designers to manage manually. Thus, a memory compiler is often used to facilitate memory designs. A typical memory compiler is a set of various, parameterized generators that can help designers to lay out memory macros, such as dynamic random access memory (DRAM) macros or static random access memory (SRAM) macros.
Conventionally, all cells in a memory layout are identical. However, in a typical memory device, the cells at edges of a memory array often have weaker electrical characteristics than their inner counterparts. One of the reasons causing the weaker edge cells is the loading effect, which refers to a phenomenon where the etch rate across a semiconductor wafer varies, as the pattern density varies over the surface of the wafer. These edge cells can have a smaller storage capacitance and driving current than those of the inner cells. In some cases, these weaker edge cells can adversely affect the yield rate of the memory devices.
As such, what is needed is a memory device with modified edge cells in order to improve its performance and overall yield rate.